Design and Implementation of an Efficient Programmable Floating Point Unit with Coarse - Grained FPGA Arun
نویسندگان
چکیده
The novel method is to optimize coarse-grained floating point units (FPUs) in a hybrid FPGA by employing common sub graph extraction to determine the number of floating point adders / subtracters (FAs), multipliers (FMs) and word blocks (WBs) in the FPUs. Single precision FP adders / subtracters (FAs) and FP multipliers (FMs), with normalization are generated using standard cell library design flow. This empirical method is used to examine the speed and area of different coarse-grained FPUs. The common sub graph extraction method is for floating point applications and tools, benchmarks and models that are used in hybrid FPGA. To explore the design of a hybrid FPGA based on common sub graph extraction and synthesis, a set of floating point designs are used as benchmark circuits. They are: (1) DSCG, a data path of digital sine-cosine generator (2) BFLY, the basic computation of Fast Fourier Transform (3) FIR 4, a 4-tap finite impulse response filter (4) ODE, a circuit to solve ordinary differential equations (5) MM 3, a 3x3 matrix multiplier (6) BGM, a circuit to compute Monte Carlo simulations of interest rate model derivatives, (7) Syn2, a circuit contains 5 FAs and 4 FMs (8) Syn7, a circuit contains 25 FAs and 25 FMs. syn2 and syn7 are two synthetic benchmark circuits generated by a synthetic benchmark circuit generator. These 8 single precision floating point benchmark circuits are not efficiently implemented in fine-grained FPGAs, since the floating point computation requires a great deal of fine-grained resources. We synthesize different combinations of floating point adders / subtracters, multipliers and registers into coarse grained blocks, which are embedded in a hybrid FPGA. Later the benchmark circuits with these coarsegrained embedded blocks (EBs) are evaluated by the Altera Quartus II Chip planner tool for area and timing analysis. [Arun. A, K. S. Srinivasan, M. Devaraju. Design and Implementation of an Efficient Programmable Floating Point Unit with Coarse-Grained FPGA. Life Sci J 2013;10(3):1959-1966] (ISSN: 1097-8135). http://www.lifesciencesite.com. 290
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